1. Field of the Invention
The present invention relates to a semiconductor device comprising a memory cell array having a hierarchical bit line structure using global bit lines and local bit lines, and a control method thereof.
2. Description of Related Art
In recent years, miniaturization of semiconductor devices such as DRAM has been achieved, and thus it has been required to reduce memory cell size by, for example, using 4F2 (F is minimum manufacturing scale) cells. Meanwhile, the number of memory cells increases with the reduction in size of memory cells, and thus bit line capacitance increases, which causes performance problems. In order to overcome the problems, a memory cell array having a hierarchical bit line structure using global bit lines and local bit lines has been employed. In such a hierarchical memory cell array, when performing a precharge operation for a bit line, a local bit line and a global bit line that should be connected to a memory cell to be accessed need to be precharged to a predetermined precharge voltage. When a differential type sense amplifier is connected to one end of the global bit line, the precharge voltage is set to an intermediate potential between, for example, HIGH and LOW levels of a read signal. A specific example of the precharge operation in the hierarchical memory cell array is disclosed, for example, in Patent Reference 1.    [Patent Reference 1] Japanese Patent Application Laid-open No. 11-096750 (U.S. Pat. No. 5,917,745)
Generally, the hierarchical memory cell array has a typical configuration in which one global bit line corresponds to a plurality of local bit lines and wiring for each local bit line is formed in a wiring layer below a wiring layer for the global bit line. Reflecting this structure, precharge lines for transmitting the precharge voltage are formed, and a precharge voltage supply circuit for generating the precharge voltage is connected to a precharge line for the global bit line in an upper layer, which is branched therefrom into a plurality of lines being connected to precharge lines for the local bit lines in a lower layer through contacts and lines. In this structure, it is undesirable to form the precharge lines for the local bit lines in the upper layer since restriction in arranging a large number of the local bit lines causes an increase in area of the memory cell array.
However, the upper wiring layer can be formed of low-resistance metallic material such as aluminum or copper, and in contrast, the lower wiring layer has to be formed of high-resistance metallic material such as tungsten or polysilicon, and space restriction makes it difficult to widen a width of the precharge lines for the local bit lines. Thus, in the precharge operation for the local bit lines, the precharge voltage is supplied to the local bit lines through the precharge lines for the local bit lines having a parasitic resistance larger than that of the precharge lines for the global bit lines, which therefore causes current supply capability for precharging to be reduced. If the width of the precharge lines for the local bit lines is widened, the current from the precharge lines for the local bit lines is supplied from the precharge lines for the global bit line through the contacts, as described above, and therefore a contact resistance thereof also causes the current supply capability for precharging to be reduced. For example, Patent Reference 1 discloses an example of the precharge operation (FIG. 7), which clearly describes that precharge operations for the global bit line and the local bit line are simultaneously performed during a predetermined period and the global bit line and the local bit line are disconnected from each other during the precharge period. That is, precharge currents are supplied individually to the global bit lines and the local bit lines through corresponding precharge lines during the precharge period. Thus, the current supply capability for precharging a plurality of local bit lines is inevitably reduced. Therefore, the precharge operation for the local bit lines through the precharge lines of high resistance is delayed relative to the precharge operation for the global bit lines through the precharge lines of low resistance. Further, the precharge voltage of the precharge lines having a low current supply capability for the local bit lines largely varies from the predetermined precharge voltage due to the parasitic resistance thereof, and a recovery time until reaching the predetermined voltage generated by the precharge voltage supply circuit increases. A variation amount of the precharge voltage depends on data (1 or 0) that has been maintained by the respective local bit lines in a read or write operation. In the severest case, all the local bit lines have maintained either of 1 or 0. In this manner, in the precharge operation of the conventional memory cell array, there is a problem that it takes a long time to stabilize the local bit lines to the precharge voltage due to factors related to wiring layout, which causes a decrease in speed in the precharge operation.